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dc.contributor.authorGimenez S.P.
dc.date.accessioned2019-08-19T23:45:28Z
dc.date.accessioned2023-05-03T20:34:55Z
dc.date.available2019-08-19T23:45:28Z
dc.date.available2023-05-03T20:34:55Z
dc.date.issued2010
dc.identifier.citationGIMENEZ, S. P.;Salvador P. Gimenez;Gimenez, S.;Gimenez, Salvador Pinillos;GIMENEZ, S.P.;GIMENEZ, SALVADOR;GIMENEZ, SALVADOR P.. Diamond MOSFET: An innovative layout to improve performance of ICs. Solid-State Electronics, v. 54, n. 12, p. 1690-1699, 2010.
dc.identifier.issn0038-1101
dc.identifier.urihttps://hdl.handle.net/20.500.12032/88908
dc.description.abstractA new planar MOSFET structure is proposed through a simple layout change, which modifies the gate geometric shape from rectangular to hexagonal in order to use the "corner effect concept" to enhance the resultant longitudinal (parallel) electric field, drift velocity of mobile carriers in the channel, drain current, transconductance, Early voltage and on-resistance in comparison to the equivalent conventional parameters. This paper is conceptual and performs a comparative analyzes between conventional and Diamond Partially-Depleted SOI nMOSFETs by 3D numerical simulations to understand the advantages and disadvantages of this innovative device compared to the conventional counterpart, keeping the same gate area, geometric factor and bias conditions. A simple analytical model for the drain current was proposed and tested for the Diamond transistor. Since we found better results of the Diamond SOI nMOSFETs we believe that, this innovative layout can be a new alternative for analog and digital integrated circuit applications for whatever area it may be needed, without any extra burden to the current technology. This layout approach can also be applied for any planar or 3D transistors technologies. © 2010 Elsevier Ltd. All rights reserved.
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.titleDiamond MOSFET: An innovative layout to improve performance of ICs
dc.typeArtigo


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