Compact diamond MOSFET model accounting for PAMDLE applicable down 150 nm node
| dc.contributor.author | Gimenez S.P. | |
| dc.contributor.author | Davini E. | |
| dc.contributor.author | Peruzzi V.V. | |
| dc.contributor.author | Renaux C. | |
| dc.contributor.author | Flandre D. | |
| dc.date.accessioned | 2019-08-19T23:45:28Z | |
| dc.date.accessioned | 2023-05-03T20:34:50Z | |
| dc.date.available | 2019-08-19T23:45:28Z | |
| dc.date.available | 2023-05-03T20:34:50Z | |
| dc.date.issued | 2014 | |
| dc.identifier.citation | GIMENEZ, S. P.; Enrico Davini Neto; Vinicius Vono Peruzzi; Christian Renaux; FLANDRE, Denis. A compact Diamond MOSFET model accounting for the PAMDLE applicable down the 150 nm node. Electronics Letters, v. 50, n. 22, p. 1618-1620, 2014. | |
| dc.identifier.issn | 0013-5194 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/88893 | |
| dc.description.abstract | © The Institution of Engineering and Technology 2014.The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) implemented with diamond layout style (hexagonal gate geometry) are quantified, thanks to the longitudinal corner effect and parallel association of MOSFETs with different channel lengths effect contributions. Futhermore, an accurate analytical drain current model for planar diamond SOI MOSFET for micrometre scale effective channel lengths is proposed and validated. The concept is then extended by 3D simulations for the 150 nm node fully-depleted SOI n-channel MOSFETs. | |
| dc.relation.ispartof | Electronics Letters | |
| dc.rights | Acesso Restrito | |
| dc.title | Compact diamond MOSFET model accounting for PAMDLE applicable down 150 nm node | |
| dc.type | Artigo |
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