Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
| dc.contributor.author | GALEMBECK, EGON H.S. | |
| dc.contributor.author | RENAUX, CHRISTIAN | |
| dc.contributor.author | FLANDRE, Denis | |
| dc.contributor.author | FINCO, SAULO | |
| dc.contributor.author | GIMENEZ, SALVADOR P. | |
| dc.date.accessioned | 2019-08-19T23:45:29Z | |
| dc.date.accessioned | 2023-05-03T20:33:14Z | |
| dc.date.available | 2019-08-19T23:45:29Z | |
| dc.date.available | 2023-05-03T20:33:14Z | |
| dc.date.issued | 2017 | |
| dc.identifier.citation | GALEMBECK, EGON H.S.; RENAUX, CHRISTIAN; FLANDRE, Denis; FINCO, SAULO; GIMENEZ, SALVADOR P.. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, v. 17, n. 1, p. 1-1, 2017. | |
| dc.identifier.issn | 1530-4388 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/88581 | |
| dc.relation.ispartof | IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | |
| dc.rights | Acesso Aberto | |
| dc.title | Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment | pt_BR |
| dc.type | Artigo | pt_BR |
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