| dc.contributor.author | Viveros-Wacher, Andrés | |
| dc.contributor.author | Baca-Baylón, Ricardo | |
| dc.contributor.author | Rangel-Patiño, Francisco E. | |
| dc.contributor.author | Dávalos-Santana, Miguel A. | |
| dc.contributor.author | Vega-Ochoa, Edgar A. | |
| dc.contributor.author | Rayas-Sánchez, José E. | |
| dc.date.accessioned | 2019-08-30T19:11:32Z | |
| dc.date.accessioned | 2023-03-21T21:08:39Z | |
| dc.date.available | 2019-08-30T19:11:32Z | |
| dc.date.available | 2023-03-21T21:08:39Z | |
| dc.date.issued | 2018-02 | |
| dc.identifier.citation | A. Viveros-Wacher, R. Baca-Baylón, F.E. Rangel-Patiño, M.A. Dávalos-Santana, E.A. Vega-Ochoa, and J.E. Rayas-Sánchez, “Jitter tolerance acceleration using the golden section optimization technique,” in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2018), Puerto Vallarta, Mexico, Feb. 2018, pp. 1-4. DOI: 10.1109/LASCAS.2018.8399908 | es |
| dc.identifier.issn | 2473-4667 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/75603 | |
| dc.description | Post-silicon validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of computer platforms under the current time-to-market (TTM) commitments. The goal of post-silicon validation for HSIO links is to confirm design robustness of both receiver (Rx) and transmitter (Tx) circuitry in a real application environment. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) through the link under worst stressing conditions. However, JTOL testing is very time-consuming when executing at specification BER, and the testing time is extremely increased when considering manufacturing process, voltage, and temperature (PVT) test coverage for a qualification decision. In order to speed up this process, we propose a new approach for JTOL testing based on the golden section algorithm. The proposed method takes advantage of the fast execution of the golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are seen. Our proposed methodology is validated by implementing it in a server HSIO link. | es |
| dc.language.iso | eng | es |
| dc.publisher | IEEE | es |
| dc.relation.ispartofseries | IEEE Latin American Symposium Circuits and Systems (LASCAS 2018); | |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf | es |
| dc.subject | Jitter | es |
| dc.subject | Jitter Tolerance | es |
| dc.subject | HSIO Link | es |
| dc.subject | Golden Section | es |
| dc.subject | Bit Error Rate | es |
| dc.subject | Post-silicon Validation | es |
| dc.title | Jitter Tolerance Acceleration Using the Golden Section Optimization Technique | es |
| dc.type | info:eu-repo/semantics/article | es |
