| dc.contributor.advisor | Aguilera-Galicia, Cuauhtémoc R. | |
| dc.contributor.author | Figueroa-Vázquez, Cristian F. | |
| dc.date.accessioned | 2020-10-14T01:16:02Z | |
| dc.date.accessioned | 2023-03-21T21:08:11Z | |
| dc.date.available | 2020-10-14T01:16:02Z | |
| dc.date.available | 2023-03-21T21:08:11Z | |
| dc.date.issued | 2020-08 | |
| dc.identifier.citation | Figueroa-Vázquez, C. F. (2020). A 0.18um CMOS linear Voltage-to-Time Converter for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle Oriented to Audio Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO | es_MX |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/75307 | |
| dc.description | This document presents a 0.18 um CMOS process highly-linear Voltage-to-Time Converter (VTC) design that can operate at a low voltage of 1.8 V across PVT corners and with the power consumption of less than 13 uW and linearity error less than 1%. The VTC was designed to work at a minimum of 1.68 V and accepts a maximum clock frequency of 900 MHz; to reduce non-linear behavior a symmetric load and current starved inverter configuration was proposed. This circuit was designed using TSMC 0.18 um CMOS process technology. | es_MX |
| dc.description.sponsorship | ITESO, A. C. | es |
| dc.language.iso | eng | es_MX |
| dc.publisher | ITESO | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | es_MX |
| dc.subject | Analog to Digital Converter | es_MX |
| dc.subject | Voltage to Time Converter | es_MX |
| dc.subject | Digital to Analog Converter | es_MX |
| dc.title | A 0.18um CMOS linear Voltage-to-Time Converter for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle Oriented to Audio Applications | es_MX |
| dc.type | info:eu-repo/semantics/academicSpecialization | es_MX |
