| dc.contributor.author | López-Félix, Carlos C. | |
| dc.date.accessioned | 2016-07-08T18:41:25Z | |
| dc.date.accessioned | 2023-03-21T21:08:05Z | |
| dc.date.available | 2016-07-08T18:41:25Z | |
| dc.date.available | 2023-03-21T21:08:05Z | |
| dc.date.issued | 2015-12 | |
| dc.identifier.citation | López-Félix, C. C. (2015). Diseño del módulo transmisor serial de datos de sistema SerDes para Protocolo PCI express 1. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO. | es |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/75260 | |
| dc.description | Serial communication protocols are developing and growing faster than any other communications protocols; this due to the economic advantages they offer because they use less communications channels, also the use of differential pairing techniques using two complementary signals that helps reduce the electromagnetic emissions and susceptibility, however, their complexity is higher than other available communications protocols. This technical report documents the design process of a serial transmitter with amplitude, pre-emphasis and programmable impedance coupling, the topology used for this implementation is the segmented self-series terminated transmitters (SSSTT) which manage the functions just described above, it does this efficiently, with low area use and lower power consumption than other conventional structures. The technology used is IBM 180nm CMOS technology (process IBM cmrf7sf) with MOSIS license. The process of design is from bottom-up methodology, because all the cells used are composed from repetitive basic cells; schematic designs were developed and tested first from basic to complex cells, using test benches. The layout of each cell is full custom; no standard cells were used because this is an analog design, despite the digital cell composition of it. For this first approach, only LVS tests were performed because individual cells are going to change their initial topology at the moment they are initially placed until the final layout site is determined, complex cells are built for the complete application. The final result was the design of a transmitter cell for one channel (+Tx) at schematic and layout level, verified with LVS test; DRC and other post layout evaluations will be performed during next design stage due to time constrains. The other channel (-Tx) is the duplication of channel +Tx. | es |
| dc.description.sponsorship | Consejo Nacional de Ciencia y Tecnología | es |
| dc.language.iso | spa | es |
| dc.publisher | ITESO, A. C. | es |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf | es |
| dc.subject | SerDes | es |
| dc.subject | SSSTT | es |
| dc.subject | Layout | es |
| dc.subject | 180 NM | es |
| dc.subject | CMOSS | es |
| dc.title | Diseño del módulo transmisor serial de datos de sistema SerDes para Protocolo PCI express 1 | es |
| dc.type | info:eu-repo/semantics/academicSpecialization | es |
