Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

Rangel-Patiño, Francisco E.; Rayas-Sánchez, José E.; Hakim, Nagib

dc.contributor.author	Rangel-Patiño, Francisco E.
dc.contributor.author	Rayas-Sánchez, José E.
dc.contributor.author	Hakim, Nagib
dc.date.accessioned	2019-08-30T19:01:23Z
dc.date.accessioned	2023-03-21T20:29:31Z
dc.date.available	2019-08-30T19:01:23Z
dc.date.available	2023-03-21T20:29:31Z
dc.date.issued	2018-10
dc.identifier.citation	F. E. Rangel-Patiño, J. E. Rayas-Sánchez, and N. Hakim, “Transmitter and receiver equalizers optimization methodologies for high-speed links in industrial computer platforms post-silicon validation,” in Int. Test Conf. (ITC-2018), Phoenix, AZ, Oct. 2018, pp. 1-10. DOI: 10.1109/TEST.2018.8624794	es
dc.identifier.issn	1089-3539
dc.identifier.uri	https://hdl.handle.net/20.500.12032/74898
dc.description	As microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over process, voltage, and temperature conditions. In addition, there is an increasingly higher number of mixed-signal circuits within microprocessors. Many of them correspond to high-speed input/output (HSIO) links. Improvements in signaling methods, circuits, and process technology have allowed HSIO data rates to scale beyond 10 Gb/s, where undesired effects can create multiple signal integrity problems. With all of these elements, post-silicon validation of HSIO links is tough and time-consuming. One of the major challenges in electrical validation of HSIO links lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel these undesired effects. Typical current industrial practices for PHY tuning require massive lab measurements, since they are based on exhaustive enumeration methods. In this work, direct and surrogate-based optimization methods, including space mapping, are proposed based on suitable objective functions to efficiently tune the transmitter and receiver equalizers. The proposed methodologies are evaluated by lab measurements on realistic industrial post-silicon validation platforms, confirming dramatic speed up in PHY tuning and substantial performance improvement.	es
dc.language.iso	eng	es
dc.publisher	IEEE	es
dc.relation.ispartofseries	International Test Conference (ITC-2018);
dc.rights.uri	http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf	es
dc.subject	Artificial Neural Networks (ANN)	es
dc.subject	Channel	es
dc.subject	Crosstalk	es
dc.subject	CTLE	es
dc.subject	DoE	es
dc.subject	Equalization	es
dc.subject	Ethernet	es
dc.subject	Eye Diagram	es
dc.subject	FIR	es
dc.subject	HSIO	es
dc.subject	ISI	es
dc.subject	Jitter	es
dc.subject	Kriging	es
dc.subject	Metamodels	es
dc.subject	Optimization	es
dc.subject	PCIe	es
dc.subject	Post-silicon Validation	es
dc.subject	Receiver	es
dc.subject	SATA	es
dc.subject	SFP	es
dc.subject	Signal Integrity	es
dc.subject	Space Mapping	es
dc.subject	Surrogates	es
dc.subject	System Margining	es
dc.subject	Transmitter	es
dc.subject	Tuning	es
dc.subject	USB	es
dc.title	Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation	es
dc.type	info:eu-repo/semantics/article	es

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