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dc.contributor.authorViveros-Wacher, Andrés
dc.contributor.authorRayas-Sánchez, José E.
dc.date.accessioned2019-08-29T18:44:29Z
dc.date.accessioned2023-03-21T19:29:50Z
dc.date.available2019-08-29T18:44:29Z
dc.date.available2023-03-21T19:29:50Z
dc.date.issued2016-12
dc.identifier.citationA. Viveros-Wacher and J. E. Rayas-Sánchez, "Eye diagram optimization based on design of experiments (DoE) to accelerate industrial testing of high speed links," 2016 IEEE MTT-S Latin America Microwave Conference (LAMC), Puerto Vallarta, 2016, pp. 1-3. doi: 10.1109/LAMC.2016.7851249es
dc.identifier.urihttps://hdl.handle.net/20.500.12032/74841
dc.descriptionHigher data rates in high speed input/output (HSIO) links demand more equalization (EQ) complexity, leading to an ever larger number of possible combinations of EQ settings. Finding the optimal set of EQ parameters through exhaustive methods is prohibitive given the time-to-market requirements. This paper presents a methodology to design a statistically sufficient set of experiments for optimizing the receiver eye diagram of a HSIO link while greatly reducing the overall testing time. Our methodology is illustrated by a 5-Gbps HSIO link comprised of a Tx, a channel (including packages, vias, PCB traces, connectors and a crosstalk aggressor) and an Rx.es
dc.language.isoenges
dc.publisherIEEEes
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes
dc.subjectEesign of Experimentses
dc.subjectEqualiserses
dc.subjectResponse Surface Methodologyes
dc.subjectTelecommunication Linkses
dc.subjectHSIO Linkes
dc.subjectHigh-speed Linkses
dc.subjectEye Diagram Optimizationes
dc.titleEye Diagram Optimization based on Design of Experiments (DoE) to Accelerate Industrial Testing of High Speed Linkses
dc.typeinfo:eu-repo/semantics/conferencePaperes


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