| dc.contributor.author | Aparicio-Zuleta, Christian | |
| dc.date.accessioned | 2019-10-09T22:24:55Z | |
| dc.date.accessioned | 2023-03-21T19:29:23Z | |
| dc.date.available | 2019-10-09T22:24:55Z | |
| dc.date.available | 2023-03-21T19:29:23Z | |
| dc.date.issued | 2019-07 | |
| dc.identifier.citation | Aparicio-Zuleta, C. (2019). Multi Language Interpreter Embedding Tool for Shift Left Pre-Silicon Validation. Trabajo de obtención de grado, Maestría en Diseño Electrónico. Tlaquepaque, Jalisco: ITESO. | es |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/74577 | |
| dc.description | Throughout the years, digital and analog designs have evolved meaningfully towards performance improvement, cost reduction and new features enablement. As a result, complexity has increased rapidly, demanding the development of better validation techniques in order to meet the time-to-market pressure calls with a bug free device. The primary choice of silicon development companies to validate software before the hardware becomes available, until now, is the FPGA based emulation platform, which leads to a big gap as it loads a register transfer level code that is usually not validated with SW-like flows in the early development stages. SW flows, mainly drivers, are validated in parallel to HW on SW emulation platforms. In order to fill the validation gap and push the finding of certain bugs to an earlier development stage, the idea of running SW tests with no or little modification in simulation environments would represent a big return of investment, rising the reliability of the system before manufacturing it, reducing time to market and development cost of the system on chip. This thesis explains the complete development of a framework able to run python scripts in VCS simulation by implementing the OVM Multi Language capability. | es |
| dc.language.iso | eng | es |
| dc.publisher | ITESO | es |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf | es |
| dc.subject | Validación Pre-Silicio | es |
| dc.subject | Diseño Lógico | es |
| dc.subject | Python | es |
| dc.subject | System Verilog | es |
| dc.subject | Simulación | es |
| dc.subject | RTL | es |
| dc.subject | System on Chip | es |
| dc.title | Multi Language Interpreter Embedding Tool for Shift Left Pre-Silicon Validation | es |
| dc.type | info:eu-repo/semantics/masterThesis | es |
