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dc.contributor.authorGodínez-Maldonado, Ricardo
dc.date.accessioned2016-08-04T17:05:30Z
dc.date.accessioned2023-03-21T18:36:09Z
dc.date.available2016-08-04T17:05:30Z
dc.date.available2023-03-21T18:36:09Z
dc.date.issued2015-12
dc.identifier.citationGodínez-Maldonado, R. (2015). Test Module Design for ITESO TV1 SerDes. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas de Chip. Tlaquepaque, Jalisco: ITESO.es
dc.identifier.urihttps://hdl.handle.net/20.500.12032/74500
dc.descriptionThis document describes the work performed from January to November 2015 on the development of the Testing Module for the ITESO TV1 SerDes chip. The objective of this project is to design, test and manufacture a SerDes (Serializer/Deserializer) system for high speed communications on a 180 nm technology using the Cadence tools for integrated circuit design. The first section describes the background of the SerDes system; this section will explain the basic architecture of a SerDes Chip, its characteristics and applications. Next, an explanation of the technology available, some testing concepts and methodologies and the specifications for designing the chip are presented. Following this, a design proposal is presented by doing a summary of the requirements gathered for the implementation of this module and a description of its functionality. After that, a description on how the Testing Module design is implemented, this section shows the RTL design specifications and verification results. Lastly, the logic and physical synthesis of this module is explained, showing the results of the verification of this finalized RTL design.es
dc.description.sponsorshipConsejo Nacional de Ciencia y Tecnologíaes
dc.language.isoenges
dc.publisherITESOes
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes
dc.subjectSerDeses
dc.subjectModule Designes
dc.titleTest Module Design for ITESO TV1 SerDeses
dc.typeinfo:eu-repo/semantics/academicSpecializationes


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