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dc.contributor.authorRangel-Patiño, Francisco E.
dc.contributor.authorRayas-Sánchez, José E.
dc.date.accessioned2022-05-13T00:11:58Z
dc.date.accessioned2023-03-21T18:09:33Z
dc.date.available2022-05-13T00:11:58Z
dc.date.available2023-03-21T18:09:33Z
dc.date.issued2022-04
dc.identifier.citationF. E. Rangel-Patiño and J. E. Rayas-Sánchez, “Surrogate-based modeling and design optimization techniques for signal integrity in high-performance computer platforms,” in Surrogate Modeling for High-Frequency Design: Recent Advances, S. Koziel and A. Pietrenko-Dabrowska, Ed., Singapore: World Scientific Pub. Europe, 2022, ch. 5, pp. 153-211.es_MX
dc.identifier.isbn978-1-80061-074-3
dc.identifier.urihttps://hdl.handle.net/20.500.12032/74377
dc.descriptionAs microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over different process, voltage, and temperature (PVT) conditions. In addition, there is an increasingly higher number of mixed-signal circuits within microprocessors; many of them employed in high-speed input/output (HSIO) links. Improvements in signaling methods, circuits, and process technology have allowed HSIO data rates to scale beyond 10 Gb/s, where undesired effects can create multiple signal integrity problems. With all of these elements, post-silicon validation of HSIO links is tough and time-consuming. One of the major challenges in post-silicon electrical validation of HSIO links lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel these undesired signal integrity effects. Typical current industrial practices for PHY tuning require massive lab measurements, since they are based on exhaustive enumeration methods. In this chapter, dedicated surrogate-based modeling and optimization methods, including space mapping, are described to efficiently tune transmitter and receiver equalizers of HSIO links. The proposed methodologies are validated by laboratory measurements on realistic industrial post-silicon validation platforms.es_MX
dc.description.sponsorshipITESO, A.C.es
dc.language.isoenges_MX
dc.publisherWorld Scientific Publishing Europees_MX
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes_MX
dc.subjectEqualizationes_MX
dc.subjectEye Diagramen
dc.subjectHigh-speed Linksen
dc.subjectJitteren
dc.subjectKrigingen
dc.subjectNeural Networksen
dc.subjectOrthogonal Arraysen
dc.subjectPhysical Layer Tuningen
dc.subjectPost-silicon Validationen
dc.subjectSATAen
dc.subjectSpace Mappingen
dc.subjectSobolen
dc.subjectSupport Vector Machinesen
dc.subjectSurrogate-based Optimizationen
dc.subjectSystem Marginingen
dc.subjectUSBen
dc.titleSurrogate-based modeling and design optimization techniques for signal integrity in high-performance computer platformses_MX
dc.typeinfo:eu-repo/semantics/bookPartes_MX


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