| dc.contributor.advisor | Pizano-Escalante, José L. | |
| dc.contributor.author | Robles-Martinez, César C. | |
| dc.date.accessioned | 2021-09-28T18:53:57Z | |
| dc.date.accessioned | 2023-03-21T18:09:25Z | |
| dc.date.available | 2021-09-28T18:53:57Z | |
| dc.date.available | 2023-03-21T18:09:25Z | |
| dc.date.issued | 2021-09 | |
| dc.identifier.citation | Robles-Martinez, C. C. (2021). Low-Cost CAN Protocol Logic Analyzer. Trabajo de obtención de grado, Maestría en Diseño Electrónico. Tlaquepaque, Jalisco: ITESO. | es_MX |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/74299 | |
| dc.description | Keeping an electronics system up to date represents a continuous challenge because technology is in constant motion. In this work, the understanding of the Field Programmable Gate Array (FPGA) technology is the central point. The most important feature of FPGA is allowing virtually the customization of any desired circuit; to perform a specific function through the usage of the hardware description Verilog language. Supported by its major benefit which is the real parallelism and high performance. The Control Area Network (CAN) protocol is a robust protocol with some strong advantages such: no master-slave scheme, differential communication, and high noise immunity, that is why this technology has a major application in the automotive field but is not limited to it. Is also used in aerospace, avionics fields, and more. Therefore, focusing on the avionics area the proposal of a low-cost CAN protocol logic analyzer is treated in this document, this analyzer aims to provide a reliable and cheaper alternative to software and tools available on the market that perform testing and debugging of Printed Circuit Boards (PCBs) or Systems, based on the CAN for communication. Besides, This tesis provides the proposal architecture and internal elements that integrates the low-cost CAN protocol logic analyzer and, generating hard saving related to PCB scrap due to the missing accurate tool to perform the CAN testing. | es_MX |
| dc.language.iso | eng | es_MX |
| dc.publisher | ITESO | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | es_MX |
| dc.subject | Analyzer | es_MX |
| dc.subject | CAN | es_MX |
| dc.subject | FPGA | es_MX |
| dc.subject | Verilog | es_MX |
| dc.title | Low-Cost CAN Protocol Logic Analyzer | es_MX |
| dc.type | info:eu-repo/semantics/masterThesis | es_MX |
