| dc.contributor.author | Lomelí-Illescas, Ismael | |
| dc.contributor.author | Solís-Bustos, Sergio A. | |
| dc.contributor.author | Martínez-Sánchez, Víctor H. | |
| dc.contributor.author | Rayas-Sánchez, José E. | |
| dc.date.accessioned | 2019-07-23T16:04:24Z | |
| dc.date.accessioned | 2023-03-21T16:19:30Z | |
| dc.date.available | 2023-03-21T16:19:30Z | |
| dc.date.issued | 2016-10 | |
| dc.identifier.citation | I. Lomelí-Illescas, S. A. Solís-Bustos, V. H. Martínez-Sánchez, and J. E. Rayas-Sánchez, “Synthesis tool for automatic layout generation of analog structures,” in IEEE ANDESCON Proc., Arequipa, Peru, Oct. 2016, pp. 1-4. | es |
| dc.identifier.isbn | 978-1-5090-2532-9 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/73543 | |
| dc.description | In this paper, a novel analog layout synthesis tool is presented. It is focused on two common analog building blocks: differential pairs and arrays of stacked devices. Starting from a circuit netlist and the names of the selected transistors, the tool verifies that these form a valid block and creates the corresponding layout. The user can define different layout parameters and the layout view can be generated with different levels of detail. Multiple layout views of a differential pair are generated to show its effectiveness to speed up the design process. | es |
| dc.language.iso | eng | es |
| dc.publisher | IEEE | es |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/TodosLosDerechosReservados.pdf | es |
| dc.subject | Analog Layout | es |
| dc.subject | Integrated Circuit | es |
| dc.subject | CAD Tool | es |
| dc.subject | Nanometric Analog Layout | es |
| dc.title | Synthesis tool for automatic layout generation of analog structures | es |
| dc.type | info:eu-repo/semantics/conferencePaper | es |
