| dc.description | This report documents the design procedure of a SerDes Transmitter module for PCI e-gen1 applications. The Transmitter module has programmable features: impedance, amplitude and pre-emphasis. Design was performed in 130nm CMOS technology (process IBM cmrf8sf). The design of the Transmitter module is divided in three stages as follow: First, a behavioral model of Transmitter module was created in Verilog-A language. This model has 2 inputs and two complementary outputs. This behavioral model was used to verify the proper system-level response of the Transmitter module alone. Simulations based on behavioral model were performed using Spectre simulator in Virtuoso-Cadence. Simulations results show that the three features: impedance, amplitude and pre-emphasis could be properly modulated with the developed Verilog-A code. The behavioral model of Transmitter module was also assembled with other modules of SerDes system in order to perform mixed-signal simulations and validate the correct response of the entire SerDes system for PCI-e gen1 specifications. As second stage, the Transmitter module was designed at transistor level with two complementary outputs. For this, we used pCells (transistors, resistors and capacitors, and vias for interconnecting devices) from CMRF8SF technology process. Transmitter module is composed by several blocks such as Mux, Decoders, basic digital cells, buffers, and pseudo-analog cells among others. Transistors of digital cells were sized by applying the basic scaling theory while transistors of pseudo-analog cells were sized by analytic calculations in an iterative way. Mux and Decoders were assembled with digital cells. To validate the correct response of each designed internal block, test-benches were created to test each block. Transient simulations were performed using Spectre in Virtuoso Cadence. After verifying the proper response of internal block alone, they were assembled to form more complex blocks such as Decoders, ZAP UNIT and others and they were also tested. Finally, all internal blocks of Transmitter module were assembled and tested at nominal PVT conditions. Critical PVT corners were evaluated and it was verified that response was under tolerance range. The third stage of design was the layout creation in a custom way. A similar bottom-up methodology followed to design at schematic-level of internal modules was applied to design the layout of each internal block of the Transmitter module. Keeping in mind the integration of internal blocks, the low–level digital cells were designed with the same height. The layout of each internal block was verified for DRC and LVS using Calibre tool and design rules of CMRF8SF process. Extraction of parasitics from layout using Calibre-PEX was done for each internal block. Post-layout response was compared to the pre-layout one; for this, Spectre simulation was performed of each internal blocks using simultaneously the extracted Calibre view and schematic view. Once the correct response was verified, the internal blocks were assembled and routed in order to build the entire layout of Transmitter module. Finally, the layout of Transmitter module was folded in order to generate the two complementary outputs. At this top level, the layout of Transmitter module was also checked for DRC and LVS. | es |
