| dc.contributor.advisor | Martínez-Guerrero, Esteban | |
| dc.contributor.author | Hernández-Flores, Jaime G. | |
| dc.date.accessioned | 2020-10-14T02:21:50Z | |
| dc.date.accessioned | 2023-03-21T15:11:42Z | |
| dc.date.available | 2020-10-14T02:21:50Z | |
| dc.date.available | 2023-03-21T15:11:42Z | |
| dc.date.issued | 2020-08 | |
| dc.identifier.citation | Hernández-Flores, J. G. (2020) Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO. | es_MX |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/73241 | |
| dc.description | This document presents the design of a time amplifier circuit in 0.18 m CMOS process with a supply voltage of 1.8 V. Simulation results performed with typical process parameters, nominal supply voltage, room temperature and an operating frequency of 200 KHz, show a time gain of 200, with an error of less than 7%. The power consumption of the designed circuit is 26 W. The circuit can receive signals with a time difference from 10 ps to 4.7 nS. The layout dimension is 149.985 m x 168.536 m, with an area of 25.3 nm2. | es_MX |
| dc.description.sponsorship | ITESO, A. C. | es |
| dc.language.iso | eng | es_MX |
| dc.publisher | ITESO | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | es_MX |
| dc.subject | Time Amplifier | es_MX |
| dc.title | Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology | es_MX |
| dc.type | info:eu-repo/semantics/academicSpecialization | es_MX |
