| dc.contributor.advisor | Martínez-Guerrero, Esteban | |
| dc.contributor.author | Martínez-Flores, Iván | |
| dc.date.accessioned | 2020-09-17T18:07:10Z | |
| dc.date.accessioned | 2023-03-21T15:11:30Z | |
| dc.date.available | 2020-09-17T18:07:10Z | |
| dc.date.available | 2023-03-21T15:11:30Z | |
| dc.date.issued | 2020-08 | |
| dc.identifier.citation | Martínez-Flores, I. (2020) A 0.18um CMOS TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle Oriented to Audio Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO. | es_MX |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/73108 | |
| dc.description | This document presents the design of an arbiter circuit for a time-based SAR-ADC. The arbiter is a TSPC D flip flop. It was designed in TSMC 0.18 μm CMOS technology with 1.8 V supply voltage. It was tested at a clock frequency of 200 KHz, but it can operate even at 100 MHz. Simulation results using the typical process parameters shown a setup time of 5.02 ps and Hold time of 51.72 ps, the TSPC D flip flop power consumption is 62.61 μW@200 KHz, and the layout area is 368.284 μm2.
The simulation is performed across all PVT corners that vary from a temperature of -40 °C up to 125 °C, with a supply voltage variation from 1.62 V up to 1.98 V and the TSPC D flip flop functionality is correct. | es_MX |
| dc.description.sponsorship | ITESO, A. C. | es |
| dc.language.iso | eng | es_MX |
| dc.publisher | ITESO | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | es_MX |
| dc.subject | TSPC | es_MX |
| dc.subject | D FF | es_MX |
| dc.subject | D Flip Flop | es_MX |
| dc.subject | Positive Edge D FF | es_MX |
| dc.title | A 0.18um CMOS TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle Oriented to Audio Applications | es_MX |
| dc.type | info:eu-repo/semantics/academicSpecialization | es_MX |
