| dc.contributor.author | Viveros-Wacher, Andrés | |
| dc.contributor.author | Baca-Baylón, Ricardo | |
| dc.contributor.author | Silva-Cortés, Johana L. | |
| dc.contributor.author | Vega-Ochoa, Edgar A. | |
| dc.contributor.author | Rayas-Sánchez, José E. | |
| dc.contributor.author | Rangel-Patiño, Francisco E. | |
| dc.date.accessioned | 2022-04-29T21:36:59Z | |
| dc.date.accessioned | 2023-03-21T15:11:26Z | |
| dc.date.available | 2022-04-29T21:36:59Z | |
| dc.date.available | 2023-03-21T15:11:26Z | |
| dc.date.issued | 2021-11 | |
| dc.identifier.citation | A. Viveros-Wacher, R. Baca-Baylón, F. E. Rangel-Patiño, J. L. Silva-Cortés, E. A. Vega-Ochoa, and J. E. Rayas-Sánchez, “Fast jitter tolerance testing for high-speed serial links in post-silicon validation,” IEEE Trans. Electromagnetic Compatibility., early access version, 2022. | es_MX |
| dc.identifier.issn | 0018-9375 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/73066 | |
| dc.description | Post-silicon electrical validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of high-performance computer platforms under current aggressive time-to-market (TTM) commitments. Improvements in signaling methods, circuits, and process technologies have allowed HSIO data rates to scale well beyond 10 Gb/s. Noise and EM effects can create multiple signal integrity problems, which are aggravated by continuously faster bus technologies. The goal of post-silicon validation for HSIO links is to ensure design robustness of both receiver (Rx) and transmitter (Tx) circuitry in real system environments. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) of the link under worst stressing conditions. However, JTOL testing is extremely time-consuming when executed at specification BER considering manufacturing process, voltage, and temperature (PVT) test coverage. In order to significantly accelerate this process, we propose a novel approach for JTOL testing based on an efficient direct search optimization methodology. Our approach exploits the fast execution of a modified golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are found. Our proposed methodology is validated in a realistic industrial server post-silicon validation platform for three different computer HSIO links: SATA, USB3, and PCIe3. | es_MX |
| dc.description.sponsorship | ITESO, A.C. | es_MX |
| dc.language.iso | eng | es_MX |
| dc.publisher | IEEE | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf | es_MX |
| dc.subject | bit error rate | es_MX |
| dc.subject | golden section | es_MX |
| dc.subject | HSIO link | es_MX |
| dc.subject | ISI | es_MX |
| dc.subject | Jitter | es_MX |
| dc.subject | jitter tolerance | es_MX |
| dc.subject | PCIe | es_MX |
| dc.subject | post-silicon validation | es_MX |
| dc.subject | SATA | es_MX |
| dc.subject | USB | es_MX |
| dc.title | Fast jitter tolerance testing for high-speed serial links in post-silicon validation | es_MX |
| dc.type | info:eu-repo/semantics/article | es_MX |
