Post-silicon validation is a crucial industrial testing process in modern computer platforms. Post-silicon validation of high-speed input/output (HSIO) links can be critical for making a product release qualification. Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry, and one of the most complex HSIO interfaces. PCIe data rates increase on every new generation. To mitigate channel effects due to the increase in transmission speeds, the PCIe specification defines requirements to perform equalization (EQ) at the transmitter (Tx) and at the receiver (Rx). During the EQ process, one combination of Tx/Rx EQ coefficients must be selected to meet the performance requirements of the system. Testing all possible coefficient combinations is prohibitive. Current industrial practice consists of finding a subset of combinations at post-silicon validation using maps of EQ coefficients, which are obtained by measuring the eye height, eye width, and the eye asymmetries of the received signal. Given the large number of electrical parameters and the multiplicity of signal eyes that are produced by on-die probes for observation, finding this subset of coefficients is often a challenge. In order to overcome this problem, a direct optimization method based on a suitable objective function formulation to efficiently tune the Tx and Rx EQ coefficients to successfully comply with the PCIe specification is presented in this report. The proposed optimization approach is based on a low-cost computational procedure combining pattern search and Nelder-Mead methods to efficiently solve an objective function with many local minima, and evaluated by lab measurements on a realistic industrial post-silicon validation platform.
