| dc.contributor.author | González-Morales, Graciela C. | |
| dc.date.accessioned | 2016-07-07T22:10:02Z | |
| dc.date.accessioned | 2023-03-16T20:09:24Z | |
| dc.date.available | 2016-07-07T22:10:02Z | |
| dc.date.available | 2023-03-16T20:09:24Z | |
| dc.date.issued | 2015-12 | |
| dc.identifier.citation | González-Morales, G. C. (2015 Diseño de módulo Serializador de un sistema SerDes para protocolo de comunicación PCI Express. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO. | es |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/72735 | |
| dc.description | This document presents the process followed for designing of a VLSI circuit, specifically the Serializer module of a SerDes used in the PCI Express protocol communication. It is shown a proposed architecture, the implementation of a RTL model in Verilog, the logic synthesis, the physical synthesis and the generation of a GDSII file for manufacturing. The Serializer of a SerDes for PCIe obtains a parallel 8 bits datum and returns a serialized 10 bit encoded datum using 8b/10b encoding. The technology used for this project is the cmrf_7sf from IBM. | es |
| dc.description.sponsorship | Consejo Nacional de Ciencia y Tecnología | es |
| dc.language.iso | spa | es |
| dc.publisher | ITESO | es |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf | es |
| dc.subject | Serializador | es |
| dc.subject | SerDes | es |
| dc.subject | VLSI | es |
| dc.subject | 180 NM | es |
| dc.title | Diseño de módulo Serializador de un sistema SerDes para protocolo de comunicación PCI Express | es |
| dc.type | info:eu-repo/semantics/academicSpecialization | es |
