| dc.contributor.author | Rayas-Sánchez, José E. | |
| dc.contributor.author | Rangel-Patiño, Francisco E. | |
| dc.contributor.author | Mercado-Casillas, Benjamin | |
| dc.contributor.author | Leal-Romo, Felipe | |
| dc.contributor.author | Chávez-Hurtado, José L. | |
| dc.date.accessioned | 2020-05-18T23:53:13Z | |
| dc.date.accessioned | 2023-03-10T17:24:42Z | |
| dc.date.available | 2020-05-18T23:53:13Z | |
| dc.date.available | 2023-03-10T17:24:42Z | |
| dc.date.issued | 2020-02-26 | |
| dc.identifier.citation | J. E. Rayas-Sánchez, F. E. Rangel-Patiño, B. Mercado-Casillas, F. Leal-Romo, and J. L. Chávez-Hurtado, Machine learning techniques and space mapping approaches to enhance signal and power integrity in high-speed links and power delivery networks. IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2020), San Jose, Costa Rica, Feb. 2020, pp.1-4. http://dx.doi.org/10.1109/LASCAS45839.2020.9068994 | es_MX |
| dc.identifier.isbn | 978-1-7281-3428-4 | |
| dc.identifier.issn | 2330-9954 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/70769 | |
| dc.description | Enhancing signal integrity (SI) and reliability in modern computer platforms heavily depends on the post-silicon validation of high-speed input/output (HSIO) links, which implies a physical layer (PHY) tuning process where equalization techniques are employed. On the other hand, the interaction between SI and power delivery networks (PDN) is becoming crucial in the computer industry, imposing the need of computationally expensive models to also ensure power integrity (PI). In this paper, surrogate-based optimization (SBO) methods, including space mapping (SM), are applied to efficiently tune equalizers in HSIO links using lab measurements on industrial post-silicon validation platforms, speeding up the PHY tuning process while enhancing eye diagram margins. Two HSIO interfaces illustrate the proposed SBO/SM techniques: USB3 Gen 1 and SATA Gen 3. Additionally, a methodology based on parameter extraction is described to develop fast PDN lumped models for low-cost SI-PI co-simulation; a dual data rate (DDR) memory sub-system illustrates this methodology. Finally, we describe a surrogate modeling methodology for efficient PDN optimization, comparing several machine learning techniques; a PDN voltage regulator with dual power rail remote sensing illustrates this last methodology. | es_MX |
| dc.description.sponsorship | ITESO, A.C. | es_MX |
| dc.language.iso | eng | es_MX |
| dc.publisher | IEEE | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf | es_MX |
| dc.subject | Broyden | es_MX |
| dc.subject | DDR | es_MX |
| dc.subject | DoE | es_MX |
| dc.subject | Equalization | es_MX |
| dc.subject | Ethernet | es_MX |
| dc.subject | Eye Diagram | es_MX |
| dc.subject | HSIO | es_MX |
| dc.subject | Impedance Profile | es_MX |
| dc.subject | Kriging | es_MX |
| dc.subject | Parameter Extraction | es_MX |
| dc.subject | PCIe | es_MX |
| dc.subject | PDN | es_MX |
| dc.subject | PHY | es_MX |
| dc.subject | Post-silicon Validation | es_MX |
| dc.subject | Power Integrity | es_MX |
| dc.subject | SATA | es_MX |
| dc.subject | Signal Integrity | es_MX |
| dc.subject | SI-PI co-simulation | es_MX |
| dc.subject | Space Mapping | es_MX |
| dc.subject | Surrogate | es_MX |
| dc.subject | System Margining | es_MX |
| dc.subject | USB | es_MX |
| dc.subject | Voltage Regulator | es_MX |
| dc.title | Machine learning techniques and space mapping approaches to enhance signal and power integrity in high-speed links and power delivery networks | es_MX |
| dc.type | info:eu-repo/semantics/conferencePaper | es_MX |
