| dc.contributor.advisor | Rayas-Sánchez, José E. | |
| dc.contributor.author | Viveros-Wacher, Andrés | |
| dc.date.accessioned | 2021-01-11T19:46:50Z | |
| dc.date.accessioned | 2023-03-10T17:16:15Z | |
| dc.date.available | 2021-01-11T19:46:50Z | |
| dc.date.available | 2023-03-10T17:16:15Z | |
| dc.date.issued | 2020-12 | |
| dc.identifier.citation | Viveros-Wacher, Andrés (2020) Machine Learning Techniques and Optimization Approaches for Analog Validation and Testing, Tesis de doctorado, Doctorado en Ciencias de la Ingeniería. Tlaquepaque, Jalisco: ITESO. | es_MX |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/70099 | |
| dc.description | Analog post-silicon validation and testing of high-speed input/output (HSIO) links in high-performance computer platforms has ever-increasing challenges caused by several factors: Moore’s law continues to advance with constant technology node miniaturization, product complexity keeps increasing along with more demanding functionalities, and data rates continue to escalate with new generations of HSIO interfaces, among others. On the other hand, there is a need to maintain aggressive product launch schedules in order to maintain market competitiveness. This scenario makes crucial for companies to find innovative solutions to accelerate validation and testing processes without sacrificing results quality. This doctoral dissertation proposes a set of machine learning and optimization methodologies aimed at improving several analog validation and testing industrial processes, most of them associated to HSIO links in modern computer platforms. It first demonstrates how receiver eye diagram margins are significantly improved by using an optimization approach based on design of experiments. It subsequently shows how the jitter tolerance test is dramatically accelerated by employing an efficient numerical optimization algorithm during execution. The present Ph.D. thesis also describes how machine learning algorithms are exploited to create surrogate models of the system under test to accelerate the physical platform tuning process during electrical post-silicon validation by using surrogate-based optimization and aggressive space mapping. Additionally, the proposed doctoral dissertation elaborates on automated analog fault identification, for which fault injection neural network models are developed by an optimization-based detection algorithm that exploits constrained parameter extraction. Finally, this Ph.D. thesis describes how deep neural network models can be properly trained to classify bit error rate (BER) extrapolation precision in margin measurements under specified BER industry standards. Each methodology proposed in this doctoral dissertation is properly validated by suitable test cases, demonstrating not only the efficiency of the proposed techniques but also the improvements to the overall analog post-silicon processes. Some future research opportunities and promising potential developments associated to analog post-silicon validation and testing are also envisioned. | es_MX |
| dc.language.iso | eng | es_MX |
| dc.publisher | ITESO | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | es_MX |
| dc.subject | Optimization | es_MX |
| dc.subject | Analog Faults | es_MX |
| dc.subject | Machine Learning | es_MX |
| dc.subject | Jitter Tolerance | es_MX |
| dc.subject | Bit Error Rate | es_MX |
| dc.title | Machine Learning Techniques and Optimization Approaches for Analog Validation and Testing | es_MX |
| dc.type | info:eu-repo/semantics/doctoralThesis | es_MX |
