| dc.contributor.author | Arrambide-Barrón, Efraín | |
| dc.date.accessioned | 2016-09-08T15:45:48Z | |
| dc.date.accessioned | 2023-03-10T16:54:42Z | |
| dc.date.available | 2016-09-08T15:45:48Z | |
| dc.date.available | 2023-03-10T16:54:42Z | |
| dc.date.issued | 2016-08 | |
| dc.identifier.citation | Arrambide-Barrón, E. (2016). Serializer Design for a SerDes chip in 130nm CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO. | es |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/69599 | |
| dc.description | This document presents the digital Serializer module description and development, which will be part of a SerDes system in 130nm CMOS technology for PCI Express protocol communication applications. The code of Serializer was written in Verilog description language, and the logical and physical synthesis were performed using the following tools, Cadence Encounter Digital Implementation System (EDI) and Encounter RTL compiler. | es |
| dc.description.sponsorship | Consejo Nacional de Ciencia y Tecnología | es |
| dc.language.iso | eng | es |
| dc.publisher | ITESO | es |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | es |
| dc.subject | SerDes | es |
| dc.subject | PCI Express | es |
| dc.subject | Serializer Architecture | es |
| dc.subject | Verilog | es |
| dc.title | Serializer Design for a SerDes chip in 130nm CMOS Technology | es |
| dc.type | info:eu-repo/semantics/academicSpecialization | es |
