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dc.contributor.advisorSilva, Marcio Rosa da
dc.contributor.authorCottens, Pablo Eduardo Pereira de Araujo
dc.date.accessioned2016-06-29T14:42:16Z
dc.date.accessioned2022-09-22T19:20:48Z
dc.date.available2016-06-29T14:42:16Z
dc.date.available2022-09-22T19:20:48Z
dc.date.issued2016-03-07
dc.identifier.urihttps://hdl.handle.net/20.500.12032/59791
dc.description.abstractCurrently, modern Artificial Neural Networks (ANN), according to their complexity, require a workstation for processing all their input data. This type of processing architecture requires that the field device is located somewhere in the vicintity of a workstation, in case real-time processing is required, or that the field device at hand will have the sole task of collecting data for future processing, when field data is required. This project creates a generic neuron architecture in programmabl logic, where Artifical Neural Networks can use the parallel nature of FPGAs to execute applications in a fast manner, albeit not using the same resolution for its otputs. This work shows that the utilization of programmable logic for the implementation of low bit resolution ANNs is not only viable, but the neural network, due to its parallel nature, benefits greatly from the hardware implementation, giving fast and accurate results.en
dc.description.sponsorshipNenhumapt_BR
dc.languagept_BRpt_BR
dc.publisherUniversidade do Vale do Rio dos Sinospt_BR
dc.rightsopenAccesspt_BR
dc.subjectFPGApt_BR
dc.subjectArtificial neural networken
dc.titleDevelopment of an artificial neural network architecture using programmable logicpt_BR
dc.typeDissertaçãopt_BR


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