| dc.description.abstract | The development of new technologies of semiconductors packaging has reduced the size of the tracks of printed circuit boards in search of miniaturization. This reduction has been reaching its own possible limits (of construction) because it has several problems, such as increase of resistance, rupture by electromigration, in addition to the increase of costs of particles control in manufacturing cleanrooms. Package on Package (PoP) comes as a proposition for encapsulation with thin chips piling in order to reduce chip occupation on the board. The difference in thermal and mechanical properties of the different materials that make up the encapsulated chip may result in the warpage of the component. In this study, the thermomechanical behavior of an electronic device encapsulated by the Package on Package technology was simulated. From the thermal and mechanical point of view, it was evaluated what factors cause the warpage of the semiconductors encapsulated with the PoP technology, warpage which is recurrent in the molding process. The manufacturing process conditions and parameters were assessed/evaluated during the making of a 40μm-thick chip prototype which was molded with a type 2 Epoxi Molding Compound - EMC - in the Materials Laboratory of Hongik University Department of Materials Science and Engineering in South Korea, our partner in this research project. Through the warpage measurements, by Moiré interferometry carried out in South Korean Hana Micron's test laboratory, we managed to build correlations with the computing simulation of this component. The results of this comparison were used as base for validation of the simulation and for adjustment of input data used in three different thickness of silicon chips (70, 100 and 200 μm) and two different EMC (EMC1 and EMC2). The manufacturing process conditions and parameters, the influence in warpage of different thicknesses and simulated components EMC types were evaluated. The simulations carried out with EMC variation in components with 40μm chip demonstrated that type 1 EMC has a decrease in warpage of the upper part of the component (Top) 42.39 percent larger than type 2 EMC. On the Top, the substract plus chip with 100 μm thickness, the warpage was reduced in 36.62 percent, and in the 200 μm chip, the reduction was by 3.29 percent. The results show the importance of simulation to predict warpage tendency, when there is the need for many variations of manufacturing production parameters. | en |
