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dc.rights.licenseLicencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC BY-NC-ND 4.0)
dc.contributor.authorMolina Robles, Roberto
dc.contributor.authorGarcía Ramírez, Ronny
dc.contributor.authorChacón Rodríguez, Alfonso
dc.contributor.authorRimolo Donadio, Renato
dc.contributor.authorArnaud Maceira, Alfredo
dc.date.accessioned2021-10-21T20:27:37Z
dc.date.accessioned2022-09-21T22:17:11Z
dc.date.available2021-10-21T20:27:37Z
dc.date.available2022-09-21T22:17:11Z
dc.date.issued2021-04
dc.identifier.urihttps://hdl.handle.net/20.500.12032/46483
dc.description.abstractThe RISC-V architecture is a very attractive option for developing application specific systems needing an affordable yet efficient central processing unit. Post-silicon validation on RISC-V applications has been done in industry for a while, however documentation is scarce. This paper proposes a practical low-cost post-silicon testing framework applied to a RISC-V RV32I based microcontroller. The framework uses FPGA-based emulation as a cornerstone to test the microcontroller before and after its fabrication. The platform only requires a handful of elements like the FPGA, a PC, the fabricated chip and some discrete components, without losing the capacity to functionally validate the design under test and save development testing time by using a re-utilize philosophy.es
dc.description.sponsorshipAgencia Nacional de Investigación e Innovación
dc.format.mimetypeapplication/pdf
dc.language.isoenes
dc.publisherIEEEes
dc.relation.ispartofIEEE Latin America Electron Devices Conference, (LAEDC), 2021.
dc.subjectPost-silicon validationes
dc.subjectTestinges
dc.subjectFPGAes
dc.subjectRISC-Ves
dc.subjectMicrocontrolleres
dc.subjectEDA toolses
dc.subjectArchitecturees
dc.subjectTest generationes
dc.subjectI/O protocolses
dc.subjectSPIes
dc.subjectTesting-plataformses
dc.titleAn affordable post-silicon testing framework applied to a RISC-V based microcontrolleres
dc.typeArtículoes


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