Diamond layout style impact on SOI MOSFET in high temperature environment

dc.contributor.author	Gimenez S.P.
dc.contributor.author	Galembeck E.H.S.
dc.contributor.author	Renaux C.
dc.contributor.author	Flandre D.
dc.date.accessioned	2019-08-19T23:45:30Z
dc.date.available	2019-08-19T23:45:30Z
dc.date.issued	2015
dc.identifier.citation	Gimenez, Salvador Pinillos; GALEMBECK, EGON HENRIQUE SALERNO; RENAUX, CHRISTIAN; FLANDRE, Denis. Diamond layout style impact on SOI MOSFET in high temperature environment. Microelectronics and Reliability, v. 55, n. 5, p. 783/MR11492-788, 2015.
dc.identifier.issn	0026-2714
dc.identifier.uri	https://repositorio.fei.edu.br/handle/FEI/1318
dc.description.abstract	© 2015 Elsevier Ltd.This work performs an experimental comparative study between the Diamond (hexagonal gate geometry) and Standard layouts styles for Metal-Oxide-Semiconductor Field Effect Transistor in high temperatures environment. The devices were manufactured with the 1 μm Silicon-on-Insulator CMOS technology. The results demonstrate that the Diamond SOI MOSFET is capable to keep active the Longitudinal Corner Effect and the Parallel Association of MOSFET with Different Channel Lengths Effect in high temperature conditions and consequently to continue presenting a better electrical performance than the one found in the conventional SOI MOSFET.
dc.relation.ispartof	Microelectronics Reliability
dc.rights	Acesso Restrito
dc.title	Diamond layout style impact on SOI MOSFET in high temperature environment
dc.type	Artigo de evento

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