Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior
| dc.contributor.author | de Souza M. | |
| dc.contributor.author | Pavanello M.A. | |
| dc.contributor.author | Martino J.A. | |
| dc.contributor.author | Simoen E. | |
| dc.contributor.author | Claeys C. | |
| dc.date.accessioned | 2019-08-19T23:45:12Z | |
| dc.date.available | 2019-08-19T23:45:12Z | |
| dc.date.issued | 2007 | |
| dc.identifier.citation | SOUZA, Michelly de; PAVANELLO, Marcelo A.;PAVANELLO, M. A.;PAVANELLO, M.;PAVANELLO, M.A.;PAVANELLO, MARCELO;ANTONIO PAVANELLO, MARCELO; MARTINO, João Antonio; SIMOEN, Eddy; CLAEYS, Cor. Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior. Microelectronic Engineering, v. 84, n. 10, p. 2121-2124, 2007. | |
| dc.identifier.issn | 0167-9317 | |
| dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/1125 | |
| dc.description.abstract | This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The maximum transconductance in linear region was used to evaluate the mobility enhancement. Besides the increased mobility provided by the strain in comparison to its unstrained SOI counterpart, higher mobility degradation for high values of applied gate voltage was observed. The subthreshold slope and the Drain Induced Barrier Lowering (DIBL) of short-channel devices have been also analyzed, showing that strained devices are more susceptible to the occurrence of short-channel effects. © 2007 Elsevier B.V. All rights reserved. | |
| dc.relation.ispartof | Microelectronic Engineering | |
| dc.rights | Acesso Restrito | |
| dc.title | Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior | |
| dc.type | Artigo |
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