Using the wave layout style to boost the digital ICs electrical performance in the radioactive environment
| dc.contributor.author | Navarenho-De-Souza R. | |
| dc.contributor.author | Silveira M.A.G. | |
| dc.contributor.author | Gimenez S.P. | |
| dc.date.accessioned | 2019-08-19T23:47:19Z | |
| dc.date.available | 2019-08-19T23:47:19Z | |
| dc.date.issued | 2015 | |
| dc.identifier.citation | NAVARENHO DE SOUZA, R.; GUAZZELI DA SILVEIRA, M.; Gimenez, S. P.. Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment. ECS Transactions (Online), v. 66, n. 5, p. 71-78, 2015. | |
| dc.identifier.issn | 1938-6737 | |
| dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/1460 | |
| dc.description.abstract | © The Electrochemical Society.This paper presents an experimental comparative study between the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) manufactured with the Wave ("S" gate geometry) and the standard layout (CnM) considering the Total Ionizing Dose (TID) effects and taking into account that the devices were biased during the radiation procedure to emphasize the effects. Due to the special layout characteristics and the different effects of the bird's beaks regions of the Wave MOSFET (WnM) compared to the conventional rectangular layout, this innovative layout proposal for MOSFETs is able to improve the device TID tolerance without adding cost to the Complementary MOS (CMOS) manufacturing process. | |
| dc.relation.ispartof | ECS Transactions | |
| dc.rights | Acesso Restrito | |
| dc.title | Using the wave layout style to boost the digital ICs electrical performance in the radioactive environment | |
| dc.type | Artigo de evento |
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