Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors
| dc.contributor.author | CONTRERAS, Esteban | |
| dc.contributor.author | CERDEIRA, Antonio | |
| dc.contributor.author | ALVARADO, Joaquin | |
| dc.contributor.author | PAVANELLO, Marcelo A. | |
| dc.date.accessioned | 2019-08-19T23:45:09Z | |
| dc.date.accessioned | 2022-09-21T19:50:06Z | |
| dc.date.available | 2019-08-19T23:45:09Z | |
| dc.date.available | 2022-09-21T19:50:06Z | |
| dc.date.issued | 2010 | |
| dc.identifier.citation | CONTRERAS, Esteban; CERDEIRA, Antonio; ALVARADO, Joaquin; PAVANELLO, Marcelo A.. Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors. JICS. Journal of Integrated Circuits and Systems (Ed. Português), v. 5, n. 2, p. 110-115, 2010. | |
| dc.identifier.issn | 1807-1953 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/40503 | |
| dc.relation.ispartof | JICS. Journal of Integrated Circuits and Systems (Ed. Português) | |
| dc.rights | Acesso Restrito | |
| dc.title | Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors | pt_BR |
| dc.type | Artigo | pt_BR |
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