| dc.contributor.author | Trevisoli R. | |
| dc.contributor.author | De Souza M. | |
| dc.contributor.author | Doria R.T. | |
| dc.contributor.author | Kilchtyska V. | |
| dc.contributor.author | Flandre D. | |
| dc.contributor.author | Pavanello M.A. | |
| dc.date.accessioned | 2019-08-19T23:45:12Z | |
| dc.date.available | 2019-08-19T23:45:12Z | |
| dc.date.issued | 2016 | |
| dc.identifier.citation | TREVISOLI, RENAN; SOUZA, Michelly de; DORIA, Rodrigo Trevisoli; KILCHYTSKA, V.; FLANDRE, D.; Pavanello, Marcelo Antonio. Junctionless nanowire transistors operation at temperatures down to 4.2 K. Semiconductor Science and Technology (Print), v. 31, p. 114001, 2016. | |
| dc.identifier.issn | 1361-6641 | |
| dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/1119 | |
| dc.description.abstract | © 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the subthreshold slope, the threshold voltage and the interface trap density are the key parameters under analysis, which has been performed through experimental results together with simulated data. Oscillations in the transconductance and output conductance have been observed in the experimental results of junctionless devices for temperatures lower than 77 K. The experimental drain current curves also exhibited a 'drain threshold voltage' for the lower temperatures. The impact of the source/drain contact resistance and discrete trap levels has been analyzed by means of simulations. | |
| dc.relation.ispartof | Semiconductor Science and Technology | |
| dc.rights | Acesso Restrito | |
| dc.title | Junctionless nanowire transistors operation at temperatures down to 4.2 K | |
| dc.type | Artigo | |
