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dc.contributor.authorDoria R.T.
dc.contributor.authorPavanello M.A.
dc.contributor.authorTrevisoli R.D.
dc.contributor.authorDe Souza M.
dc.contributor.authorLee C.-W.
dc.contributor.authorFerain I.
dc.contributor.authorAkhavan N.D.
dc.contributor.authorYan R.
dc.contributor.authorRazavi P.
dc.contributor.authorYu R.
dc.contributor.authorKranti A.
dc.contributor.authorColinge J.-P.
dc.identifier.citationDORIA, Rodrigo Trevisoli; YU, R.; KRANTI, Abhinav; COLINGE, J. -P.; PAVANELLO, Marcelo A.; Pavanello, Marcelo Antonio; TREVISOLI, Renan Doria; DE SOUZA, Michelly; LEE, C. W.; FERAIN, Isabelle; DEHDASHTI-AKHAVAN, N.; YAN, R.; RAZAVI, P.. Junctionless Multiple-Gate Transistors for Analog Applications. I.E.E.E. Transactions on Electron Devices, v. 58, n. 8, p. 2511-2519, 2011.
dc.description.abstractThis paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors. © 2010 IEEE.
dc.relation.ispartofIEEE Transactions on Electron Devices
dc.rightsAcesso Restrito
dc.titleJunctionless multiple-gate transistors for analog applications

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