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dc.contributor.authorGimenez S.P.
dc.contributor.authorAlati D.M.
dc.contributor.authorSimoen E.
dc.contributor.authorClaeys C.
dc.date.accessioned2019-08-19T23:45:28Z
dc.date.available2019-08-19T23:45:28Z
dc.date.issued2011
dc.identifier.citationGimenez, Salvador Pinillos; Alati, Daniel Manha; Simoen, Eddy; Claeys, Cor. FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs. Journal of the Electrochemical Society, v. 158, n. 12, p. H1258-H1264, 2011.
dc.identifier.issn0013-4651
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1301
dc.description.abstractThis paper is conceptual and introduces a new transistor layout style called FISH SOI MOSFET (FSM). It is an evolution of the Diamond device (DSM) and specially designed to preserve the Longitudinal Corner Effect (LCE) to increase the resultant longitudinal electric field along the channel, that results in an improvement in the average carrier drift velocity in the channel. It presents a gate geometric shape similar to a n"smaller than" (<) mathematical symbol. Unlike the DSM, the FISH layout style brings an innovative possibility in the "lengthening of its effective channel length, defined as Lengthening of Effective Channel Length Effect (LECLE)", keeping the channel length with the minimum dimension allowed by the SOI CMOS process technology used in manufacturing digital ICs applications. It can reduce the die area of digital ICs by using the LECLE of the FISH layout structure style by combining conventional SOI pMOSFETs and FISH nMOSFETs. Thanks to the FSM LECLE, one also can reduce the die area of the current mirrors of analog integrated circuits. For the first time, it is shown that LECLE in the FSM structure is able to increase the Early voltage and consequently to improve significantly the voltage gain of analog ICs. © 2011 The Electrochemical Society.
dc.relation.ispartofJournal of the Electrochemical Society
dc.rightsAcesso Restrito
dc.titleFISH SOI MOSFET: Modeling, characterization and its application to improve the performance of analog ICs
dc.typeArtigo


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