dc.contributor.author | Pavanello M.A. | |
dc.contributor.author | Der Agopian P.G. | |
dc.contributor.author | Martino J.A. | |
dc.contributor.author | Flandre D. | |
dc.date.accessioned | 2019-08-19T23:45:08Z | |
dc.date.available | 2019-08-19T23:45:08Z | |
dc.date.issued | 2006 | |
dc.identifier.citation | PAVANELLO, Marcelo A.; AGOPIAN, Paula Ghedini Der; MARTINO, João Antonio; FLANDRE, Denis. Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications. Microelectronics Journal, v. 37, n. 2, p. 137-144, 2006. | |
dc.identifier.issn | 0026-2692 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/1060 | |
dc.description.abstract | We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a comparison between the results obtained by two-dimensional numerical simulations and measurements in the whole temperature range under study. The Graded-Channel transistor presents higher Early voltage if compared to the conventional fully depleted SOI nMOSFET, without degrading the transconductance over drain current, at all studied temperatures, leading to a gain larger than 20 dB compared to the conventional SOI. The resulting higher gain lies in the improvement of the electric field distribution and impact ionization rate by the graded-channel structure. © 2005 Elsevier Ltd. All reserved. | |
dc.relation.ispartof | Microelectronics Journal | |
dc.rights | Acesso Restrito | |
dc.title | Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications | |
dc.type | Artigo | |