| dc.contributor.author | Trevisoli R.D. | |
| dc.contributor.author | Doria R.T. | |
| dc.contributor.author | De Souza M. | |
| dc.contributor.author | Pavanello M.A. | |
| dc.date.accessioned | 2019-08-19T23:45:10Z | |
| dc.date.available | 2019-08-19T23:45:10Z | |
| dc.date.issued | 2011 | |
| dc.identifier.citation | TREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; PAVANELLO, Marcelo A.; Pavanello, Marcelo Antonio. Threshold voltage in junctionless nanowire transistors. Semiconductor Science and Technology (Print), v. 26, p. 105009, 2011. | |
| dc.identifier.issn | 0268-1242 | |
| dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/1091 | |
| dc.description.abstract | This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the dependence on JNT width, height and doping concentration. The quantum confinement has also been taken into consideration in the model formulation. The model is validated using experimental results of nMOS and pMOS JNTs, and three-dimensional TCAD simulations where the nanowire width and height, doping concentration, gate oxide thickness and temperature have been varied. The gate oxide capacitance is also addressed aiming to adequately calculate the capacitance in non-planar devices. The temperature influence on the threshold voltage of JNTs is also analyzed. The presented model shows excellent agreement with both experimental and simulated data, adequately describing the JNT threshold voltage. © 2011 IOP Publishing Ltd. | |
| dc.relation.ispartof | Semiconductor Science and Technology | |
| dc.rights | Acesso Restrito | |
| dc.title | Threshold voltage in junctionless nanowire transistors | |
| dc.type | Artigo | |
