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3D simulation of triple-gate MOSFETs with different mobility regions
(2011-07-05)
In this paper we present a new approach for analyzing 3D structure triple-gate MOSFETs using three different regions, one at the top and two in the sidewalls of the fin, which allows for considering different carrier ...
Experimental evaluation of mismatching on the analog characteristics of GC SOI MOSFETs
(2017-07-28)
This paper presents an experimental study of mismatching on the analog characteristics of fully-depleted graded-channel SOI MOSFET in comparison to uniformly doped transistors. The study is carried out using dedicated ...
Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors
(2011-10-11)
In this work an asymmetric self-cascode (SC) structure implemented in a 150nm technology have been studied as a function of the threshold voltage and length of both transistors in the structure, aiming to improve the analog ...
Study of matching properties of graded-channel SOI MOSFETs
(2008-01-05)
In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching ...