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Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures
(2009)
This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of ...
Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer
(2008)
In this work the performance of graded-channel (GC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with GC ...
Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior
(2007)
This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The ...
Junctionless nanowire transistors parameters extraction based on drain current measurements
(2019)
© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As ...
Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors
(2016)
© The Institution of Engineering and Technology 2016.In this paper, the performance of asymmetric self-cascode (A-SC) fully depleted silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors ...
Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
(2017)
© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. ...
Modeling of thin-film lateral SOI PIN diodes with an alternative multi-branch explicit current model
(2012)
We propose the use of an alternative multi-exponential model to describe multiple conduction mechanisms in thin-film SOI PIN diodes with parasitic series resistance over a wide operating temperature range, from 90 to 390 ...
Physical insights on the dynamic response of SOI n-and p-type junctionless nanowire transistors
(2018)
© 2018, Brazilian Microelectronics Society. All rights reserved.— This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p-and n-type Junctionless ...