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Now showing items 11-19 of 19
Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors
(2013)
A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 10 19 cm-3, as well as ...
Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs
(2013)
In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried ...
Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
(2016)
© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped ...
Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors
(2014)
This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, ...
Trap density characterization through low-frequency noise in junctionless transistors
(2013)
This work evaluates, for the first time, the trap density of Junctionless Nanowire Transistors (JNTs) of two technologies produced with different gate dielectrics through the low-frequency noise (LFN) characterization. ...
Substrate bias influence on the operation of junctionless nanowire transistors
(2014)
The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, ...
Approximate analytical expression for the tersminal voltage in multi-exponential diode models
(2013)
We propose a simple approximate solution for the terminal voltage as an explicit function of the terminal current for diodes which need to be modeled by two or more ideal diodes in parallel. As a result, this solution is ...
Analysis of the leakage current in junctionless nanowire transistors
(2013)
This letter presents an analysis of the leakage current in Junctionless Nanowire Transistors. The analysis is performed using experimental data together with three-dimensional numerical simulations. The influences of the ...
Cryogenic operation of junctionless nanowire transistors
(2011)
This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and ...