Implementation and Evaluation of Branch Predictors on RISC-V

Abstract

This work studies three branch prediction schemes for a pipelined RV32I core with a Reorder Buffer: an N-bit counter, a Global History Register (GHR) indexed counter array, and Gshare. The design integrates a Branch Target Buffer split into unconditional and conditional structures. Each predictor is modeled in C++ using the CBP 2016 framework to measure MPKI under an 8 KB storage budget. The algorithms are implemented in SystemVerilog, integrated into the RTL, and synthesized on an Intel MAX 10 FPGA. We also document a reproducible bare-metal build and load flow for C code: cross-compilation, linker script setup, memory image generation, and RTL loading. RTL simulation evaluates IPC and total cycles on Dhrystone, Qsort, and CoreMark workloads.

C++ results show that Gshare reduces MPKI by 85.25% relative to a No BPU baseline with the same storage and outperforms GHR using the same counter and index settings. RTL results with a 15-bit index for simulation (7-bit index in synthesis due to resources) confirm the trend. Averaged across the three workloads, Gshare improves MPKI by 62.77%, IPC by 17.44%, and total cycles by 14.23% versus No BPU. Synthesis reports show modest hardware cost compared to baseline (about 38–40% more logic elements) and a small reduction in Fmax (about 8–10%). The results indicate that simple global-history predictors, and in particular Gshare, provide large accuracy and performance gains with minimal architectural complexity.