Implementation of a Hash Security Algorithm using an ARM Cortex M3 Soft Core

Abstract

This work presents the implementation of the SHA-3-512 hash algorithm on an ARM Cortex-M3 soft core deployed on an Xilinx Artix-7 FPGA. Initially, we introduce hash algorithms, outlining their role in ensuring data integrity, authentication, and security in various applications, including cryptography, digital signatures, and blockchain technology. We then delve into the inner workings of SHA-3-512, a member of the Keccak family, emphasizing its sponge construction and robust resistance to collision attacks, making it one of the most secure hash algorithms. The study details the acquisition of the ARM Cortex-M3 softcore from ARM’s DesignStart program, including modifications to streamline the softcore by removing unneeded peripherals and optimizing it for our specific application. Two implementations are developed: a pure software implementation, executed entirely on the ARM Cortex-M3, and a mixed hardware-software co-processor design that leverages the FPGA’s parallel processing capabilities to enhance performance. We compare the performance and resource utilization of both implementations, analyzing metrics such as execution time, power consumption, and FPGA resource usage. The results demonstrate that the mixed hardware-software co-processor achieves a performance improvement of 161 times that of the pure software implementation while maintaining efficient resource utilization. This case study highlights the advantages of hardware acceleration in cryptographic applications and provides insights into optimizing hash algorithm implementations on resource- constrained embedded systems.