| dc.contributor.author | Rangel-Patiño, Francisco E. | |
| dc.contributor.author | Viveros-Wacher, Andres | |
| dc.contributor.author | Rajyaguru, Chintan | |
| dc.contributor.author | Vega-Ochoa, Edgar A. | |
| dc.contributor.author | Rodriguez-Saenz, Sofia D. | |
| dc.contributor.author | Silva-Cortes, Johana L. | |
| dc.contributor.author | Shival, Hemanth | |
| dc.contributor.author | Rayas-Sánchez, José E. | |
| dc.date.accessioned | 2023-08-14T22:59:24Z | |
| dc.date.accessioned | 2025-03-26T14:10:15Z | |
| dc.date.available | 2023-08-14T22:59:24Z | |
| dc.date.available | 2025-03-26T14:10:15Z | |
| dc.date.issued | 2023-06-14 | |
| dc.identifier.citation | F. E. Rangel-Patiño, A. Viveros-Wacher, C. Rajyaguru, E. A. Vega-Ochoa, S. D. Rodriguez-Saenz, J. L. Silva-Cortes, H. Shival, and J. E. Rayas-Sánchez, “Equalization tuning of the PCIe physical layer by using machine learning in industrial post-silicon validation,” in IEEE MTT-S Int. Microwave Symp. Dig., San Diego, CA, Jun. 2023, pp. 628. | es_MX |
| dc.identifier.isbn | 978-1-6654-9614-8 | |
| dc.identifier.issn | 2575-4742 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/160419 | |
| dc.description | The increasing complexity of high-speed computer platforms has made post-silicon validation a highly demanding industrial task. A large portion of the circuits to be validated in modern microprocessors corresponds to high-speed input/output (HSIO) links, imposing the need to efficiently tune the transmitter (Tx) and receiver (Rx) equalizers. In this work, we first use unsupervised machine learning techniques to cluster all available post-silicon data from different channels, dividing them into distinct sets of channel conditions. We then develop statistical supervised machine learning models, based on Gaussian process regression (GPR), to predict the eye diagram margins within each data subset. We finally optimize the GPR-based models to obtain the optimal tuning settings for the specific channels. Our proposed method is validated by measurements of the functional eye diagram of an actual industrial computer platform. | es_MX |
| dc.description.sponsorship | ITESO, A.C. | es |
| dc.language.iso | eng | es_MX |
| dc.publisher | IEEE | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf | es_MX |
| dc.subject | PCIe, equalization, post-silicon validation, machine learning, clustering, Gaussian process regression | es_MX |
| dc.subject | PCIe | es_MX |
| dc.subject | Equalization | es_MX |
| dc.subject | Post-silicon Validation | es_MX |
| dc.subject | Machine Learning | es_MX |
| dc.subject | Clustering | es_MX |
| dc.subject | Gaussian Process Regression | es_MX |
| dc.title | Equalization Tuning of the PCIe Physical Layer by Using Machine Learning in Industrial Post-silicon Validation | es_MX |
| dc.type | info:eu-repo/semantics/conferencePaper | es_MX |
| dc.type.version | info:eu-repo/semantics/publishedVersion | es_MX |
