Compute Express Link Optimization for Low Latency

Abstract

This thesis delves into the architecture of the Compute Express Link® (CXL®) 1.1 specification, which is built on top of the physical and electrical interface of the peripheral component interconnect express® (PCIe®) Gen 5. CXL is a technology focused on efficiently handling generative artificial intelligence (AI) and its enormous memory performance demands. CXL enables coherency between the central processing unit (CPU) memory space and memory connected under devices for memory pooling. As CXL technology gains traction, optimizing latency has become a significant area for improvement. Fortunately, new configurations are available that can improve the user experience for advanced workloads. One way to reduce latency is to use the equalization process in fixed mode during CXL link bring-up and avoid recoveries or retries under the link training state machine (LTSSM) setup that are continuously triggered due to the bit error. Some equalizers are subject to operate in dynamic mode and require real-time latency optimization. The purpose of this thesis is to demonstrate the advantages and disadvantages of different optimization methods using latency measurement tools that are applicable only on the CXL validation stage. The study also utilizes optimization techniques implemented in MATLAB to determine the minimum global solution of an objective function. This research suggests that creating tools that can monitor, analyze, and control the optimal CXL link latency can contribute and improve significantly to future CXL technology implementations.