| dc.contributor.advisor | Longoria-Gándara, Omar H. | |
| dc.contributor.author | Hernández-Reyes, Federico J. | |
| dc.date.accessioned | 2024-02-02T23:00:09Z | |
| dc.date.accessioned | 2024-02-27T18:50:25Z | |
| dc.date.available | 2024-02-02T23:00:09Z | |
| dc.date.available | 2024-02-27T18:50:25Z | |
| dc.date.issued | 2023-10 | |
| dc.identifier.citation | Hernández-Reyes, F. J. (2023). Post-Silicon Functional Validation of a DDR5 Memory Controller. Trabajo de obtención de grado, Maestría en Diseño Electrónico. Tlaquepaque, Jalisco: ITESO. | es_MX |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/122476 | |
| dc.description | A case study of the application of a post-silicon functional validation methodology to the validation of a DDR5 memory controller is presented. The work is in the context of the post-silicon validation of the Next Generation Intel® Xeon Server CPU.
The post-silicon functional validation methodology is presented not as a novel approach to validation but to set the context for the description of how the different phases of the methodology were applied to the functional validation of a DDR5 memory controller which features technological advances in DDR5 frequencies up to 6400MT/s and Multiplexed Combined Rank DIMMs that achieve 30-40% more bandwidth than regular RDIMMs, new RAS characteristics and performance-driven architectural improvements. It also serves as guide for future applications of the methodology on the validation of different technologies or IPs.
The results of the validation of the DDR5 memory controller are presented and discussed for each of the phases of the methodology starting with the validation strategy centered in defining the HW and SW configurations aimed to cover all the functional features of the memory controller; the test content development and the debug strategies are also described. The utilization of Virtual Platforms and Emulation systems as a vehicle to verify the test content was ready and met its intent and the execution results in this stage are covered. Then, the results of the execution of the test plan in the actual post-silicon phases of power-on and volume validation execution are considered under the light of the number of silicon, architectural, BIOS and FW bugs found.
Finally, the evaluation of the project using number of bugs and time to market metrics is discussed. Areas of improvement for the post-silicon validation execution are identified and proposed as learnings to the next project. | es_MX |
| dc.language.iso | eng | es_MX |
| dc.publisher | ITESO | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | es_MX |
| dc.subject | Post-Silicon | es_MX |
| dc.subject | Functional Validation | es_MX |
| dc.subject | Memory Controller | es_MX |
| dc.title | Post-Silicon Functional Validation of a DDR5 Memory Controller | es_MX |
| dc.type | info:eu-repo/semantics/masterThesis | es_MX |
