Diseño e implementación de un procesador IP CORE en un dispositivo de lógica programable FPGA
| dc.contributor.advisor | García Vargas, Luisa Fernanda | |
| dc.contributor.author | Viveros Rocha, Anamaría | |
| dc.date.accessioned | 2014-04-22T16:45:56Z | |
| dc.date.accessioned | 2014-10-09T04:20:47Z | |
| dc.date.accessioned | 2016-03-29T17:50:52Z | |
| dc.date.accessioned | 2020-04-16T16:31:57Z | |
| dc.date.accessioned | 2023-05-11T17:26:11Z | |
| dc.date.available | 2014-04-22T16:45:56Z | |
| dc.date.available | 2014-10-09T04:20:47Z | |
| dc.date.available | 2016-03-29T17:50:52Z | |
| dc.date.available | 2020-04-16T16:31:57Z | |
| dc.date.available | 2023-05-11T17:26:11Z | |
| dc.date.created | 2010 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/108388 | |
| dc.format | spa | |
| dc.format.mimetype | application/pdf | spa |
| dc.language.iso | spa | spa |
| dc.publisher | Pontificia Universidad Javeriana | spa |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
| dc.subject | Validación de programas para computador | spa |
| dc.subject | Programación (Computadores electrónicos) | spa |
| dc.subject | Matrices lógicas programables | spa |
| dc.title | Diseño e implementación de un procesador IP CORE en un dispositivo de lógica programable FPGA | spa |
Files in this item
| Files | Size | Format | View |
|---|---|---|---|
| tesis469.pdf | 1.906Mb | application/pdf | View/ |
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Except where otherwise noted, this item's license is described as http://creativecommons.org/licenses/by-nc-nd/4.0/