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Hierarchical modeling and control for reentrant semiconductor fabrication lines: a mini-fab benchmark

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dc.creator FLORES GODOY, JOSE JOB; 31306
dc.creator FLORES GODOY, JOSE JOB
dc.creator TSAKALIS S., KONSTANTINOS
dc.creator RODRIGUEZ, ARMANDO A.
dc.date.accessioned 2018-07-17T14:45:14Z
dc.date.accessioned 2018-08-30T16:04:51Z
dc.date.available 2018-07-17T14:45:14Z
dc.date.available 2018-08-30T16:04:51Z
dc.date.created 2018-07-17T14:45:14Z
dc.date.issued 1997
dc.identifier http://ri.ibero.mx/handle/ibero/1746
dc.identifier FGJJ_Conf_06
dc.identifier.uri http://hdl.handle.net/20.500.12032/474825
dc.language eng
dc.relation https://ieeexplore.ieee.org/document/616323/
dc.relation https://www.researchgate.net/publication/3708932_Hierarchical_modeling_and_control_for_re-entrant_semiconductor_fabrication_lines_a_mini-fab_benchmark?enrichId=rgreq-6540a4459cac749cfab41d82c89a3ac1-XXX&enrichSource=Y292ZXJQYWdlOzM3MDg5MzI7QVM6MjkxODM2OTkzMjYxNTY4QDE0NDY1OTA3NjkyNjU%3D&el=1_x_2&_esc=publicationCoverPdf
dc.rights http://creativecommons.org/licenses/by-nc-nd/4.0
dc.rights openAccess
dc.source IEEE 6th International Conference on Emerging Technologies and Factory Automation Proceedings, EFTA '97
dc.title Hierarchical modeling and control for reentrant semiconductor fabrication lines: a mini-fab benchmark
dc.type Ítem publicado en memoria de congreso


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