| dc.rights.license | Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC BY-NC-ND 4.0) | |
| dc.contributor.author | Gak Szollosy, Joel | |
| dc.contributor.author | Arnaud Maceira, Alfredo | |
| dc.contributor.author | Miguez de Mori, Matías Rafael | |
| dc.date.accessioned | 2021-10-21T21:21:20Z | |
| dc.date.accessioned | 2022-09-21T22:20:33Z | |
| dc.date.available | 2021-10-21T21:21:20Z | |
| dc.date.available | 2022-09-21T22:20:33Z | |
| dc.date.issued | 2021 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/46751 | |
| dc.description.abstract | A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 lm CMOS-HV technology, is presented. This family of circuits have a special interest in the case of implantable medical devices where is common to handle previously unknown voltages either positive or negative, above or below the control logic supply VDD. Two application examples are presented: a composite switch to control negative stimuli voltage pulses, and a multi-channel programmable charge-pump voltage multiplier, aimed at charging the output capacitors of an IMD. | es |
| dc.description.sponsorship | Agencia Nacional de Investigación e Innovación | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en | es |
| dc.publisher | Springer | es |
| dc.relation.ispartof | Analog Integrated Circuits and Signal Processing, Vol.3, No. 107, pp. 617–628, 2021. | |
| dc.subject | Level shifter | es |
| dc.subject | HV-CMOS | es |
| dc.subject | Biomedical circuits | es |
| dc.title | CMOS level shifters from 0 to 18 V output | es |
| dc.type | Artículo | es |
