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dc.contributor.authorTrevisoli R.
dc.contributor.authorDoria R.T.
dc.contributor.authorde Souza M.
dc.contributor.authorBarraud S.
dc.contributor.authorPavanello M.A.
dc.date.accessioned2019-08-19T23:45:13Z
dc.date.available2019-08-19T23:45:13Z
dc.date.issued2019
dc.identifier.citationTREVISOLI, Renan D.; DORIA, R. T.; DE SOUZA, Michelly; BARRAUD, S.; PAVANELLO, M. A.. Junctionless Nanowire Transistors Parameters Extraction Based on Drain Current Measurements. SOLID-STATE ELECTRONICS, v. 158, p. 37-45, 2019.
dc.identifier.issn0038-1101
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1140
dc.description.abstract© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices.
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.titleJunctionless nanowire transistors parameters extraction based on drain current measurements
dc.typeArtigo


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